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sin o wealth SH86270 h ighly - integrated d igital m usic soc pr elimin ary ver 0. 91 feb 7 , 200 7 information in this document is provided in relation to sino wealth products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in sino wealth products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty o f any kind. s ino wealth e lectronic reserves the right to change products or specification without notice.
sino wealth sh862 7 0 200 7/2/7 2 / 11 ver 0. 91 content 1. features ................................ ................................ ................................ ................................ .. 3 2. general description ................................ ................................ ................................ ...... 4 3. pad & pin assignment ................................ ................................ ................................ ....... 5 3.1. m ain c hip p in a ssignment ( lqfp 64) ................................ ................................ ................ 5 3.2. pad & pin d escription ................................ ................................ ................................ ..... 7 4. electrical specifica tions ................................ ................................ ........................ 10 4.1. dc c haracteristics ................................ ................................ ................................ ......... 10 4.2. ac c haracteristics ................................ ................................ ................................ ......... 10 5. package outline ................................ ................................ ................................ ............. 11 5.1. lqfp64 o utline ( for m ain c hip p ackage ) ................................ ................................ .... 11
sino wealth sh862 7 0 200 7/2/7 3 / 11 ver 0. 91 1. features ? single - cycle 8051 cpu core: - internal adjustable operation frequency (1/6/12/15/27/33.75mhz) for energy saving. - 12k - byte program sram, 256 - byte internal data sram and 128 - byte sfr. - 7k - byte external data sram. ? fu lly compatible with full - speed usb2.0 specification: - support one device address. - support 3 endpoints: one control endpoint, one bulk - in endpoint and one bulk - out endpoint. ? built - in nand f lash c ontroller : - flexible engine for s lc and mlc nand flash ( including nand flash memories by samsung, toshiba , hynix, st, micron and other types . ) ? built - in mmc/sd card engine. ? built - in lcd module interface: - support 8080 compatible lcd interface byte parallel mode and serial mode. - supp ort bit antitone. - support ht1621 (32x4) interface. ? built - in mpeg audio decoder: - support 8/11.025/12/16/22.05/24/32/44.1/48khz sampling frequencies for mpeg bit stream. - support 32/40/48/56/64/80/96/112/128/160/192/224/256/320 k bps bit rate for mpeg1 . - support 8/16/24/32/40/48/56/64/80/96/112/128/144/160 k bps bit rates for mpeg2 . - support 8/16/24/32/40/48/56/64/80/96/112/128/144/160 k bps bit rates for mpeg2.5 . - support single channel, dual channel and stereo format. - eq effects support natural/pop/rock/classic/jazz/ string/hp - enhance/reggae/extra - bass sound effects. ? on - chip codec: - 16 - bit sigma - delta stereo dac for audio play. - 8 - bit adc for voice record and battery v oltage d etect ion. - fm - in for external fm module. - s tereo headphone amplifier . h eadphone driver output with short - circuit protected . ? built - in one 16 - bit timer. ? 12mhz external clock input with on - chip pll . ? low power 1.8v core operation voltage and 3.3v i/o operation voltage. ? built - in dc/dc ? support t wo p ower m anagement m ode: idle mode and stop mode. ? power consump tion below 4 5mw (while decoding 128kbps @44.1khz mpeg audio bit stream ) . ? four r eset source s : - power - o n r eset (por) . - lower v oltage r eset (lvr) . - watchdog r eset (wdr) . - external pin reset (epr) . ? available in lqfp 64 (10mm x 10mm) package , qfp100 (14mm x 20mm) pac kage and cob.
sino wealth sh862 7 0 200 7/2/7 4 / 11 ver 0. 91 2. general description the SH86270 is a single - cycle 8051 cpu core embedded device with a powerful flash card/memory controller and mpeg audio decoder. it includes a single - cycle 8051 cpu core, usb2.0 full - speed sie and phy functional block, on e adc and one dac, a mpeg audio decoder and relevant interfaces in lqfp64 package. SH86270 is really suitable for any data storage related products, i.e. full - speed usb2.0 flash disk, portable mpeg audio player, card reader/writer, etc.
sino wealth sh862 7 0 200 7/2/7 5 / 11 ver 0. 91 3. pad & pin assignment 3.1. main chip pin assignment ( lqfp 64) figure 1 . main chip pin assignment ( lqfp 64)
sino wealth sh862 7 0 200 7/2/7 6 / 11 ver 0. 91 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 voutrhp 17 vdd18 33 pa3 49 efale 2 avddhp 18 vddio 34 pa4 50 efcle 3 vrefhp 19 vdd3 35 pa5 51 d0 4 agndhp 20 dp 36 pa6 5 2 d1 5 voutlhp 21 dm 37 pa7 53 d2 6 test 22 vssio 38 vdd18 54 d3 7 lx_v3 23 usbdet 39 pc3 55 d4 8 gnd 24 x12mout 40 pc2 56 d5 9 lx_v18 25 x12min 41 pc1 57 d6 10 vref 26 vss 42 pc0 58 d7 11 vbat _in 27 resetn 43 lcmcsn 59 vinlfm 12 vinbat 28 pb0 44 e frdy 60 vinmic 13 dc _ mod e 0 29 pb1 45 efren 61 vinrfm 14 dc _ mod e 1 30 pa0 46 efwen 62 vref dac 15 vout_v3 31 pa1 47 efce1n 63 agnd 16 vout_v18 32 pa2 48 efce0n 64 avdd table 1 . main chip with built - in dc/dc pin assignment ( lqfp 64)
sino wealth sh862 7 0 200 7/2/7 7 / 11 ver 0. 91 3.2. pad & pin description pin no. category pad no. pad name type state i dr /i si description ev mc dac 1 voutrhp o - - headphone output right 5 1 dac 2 avddhp p - - headphone supply voltage 6 2 dac 3 vrefhp o - - headphone reference voltage 7 3 dac 4 agndhp p - - headphone ground 8 4 dac 5 voutlhp o - - headphone output left 9 5 system 6 test i pl - test mode 10 6 gpio 7 pb2 i/o cp 1ma general purpose i/o pin 11 - system 8 vss p - - d igital ground of rom 12 gnd 9 dc/dc 10 lx_v3 o - - pin for switc hing 3v power 13 7 11 12 dc/dc 13 gnd p - - dc/dc d igital ground 14 8 14 dc/dc 15 lx_v18 o - - pin for switching 1.8 v power 15 9 dc/dc 16 vref i - - reference voltage input 16 10 dc/dc 17 vbat _in p - - 1xaa, 1xaaa battery v oltage i nput 17 11 adc 18 vinbat i - - battery voltage input 18 12 dc/dc 19 dc _ mod e 0 i - - dc/dc mode select 0 19 13 dc/dc 20 dc _ mod e 1 i - - dc/dc mode select 1 20 14 dc/dc 21 tmode0 i - - dc/dc test pad 21 - dc/dc 22 tmode1 i - - dc/dc test pad 22 - 23 dc/dc 24 vout_v3 o - - 3v voltage output 23 15 25 dc/dc 26 vout_v18 o - - 1.8 v voltage output 29 16 27 system 28 vdd18 p - - 1.8 v supply voltage for core circuit 30 17 dc/dc 29 tpin4 i/o - - dc/dc test pad 31 - dc/dc 30 tpin2 i/o - - dc/dc test pad 32 - dc/dc 31 tpin3 i/o - - dc/dc test pad 33 - dc/dc 32 tpin1 i/o - - dc/dc test pad 34 - system 33 vddio p - - 3v supply voltage for peripheral circuit 35 18 system 34 vdd3 p - - 3v supply voltage for core circui t 36 19 usb 35 dp i/o - - usb data in data positive pin terminal 37 20 usb 36 dm i/o - - usb data in data negative pin terminal 38 21 37 system 38 vssio p - - d igital ground of 3v peripheral circuit 39 22 usb 39 vddusbpu o - - usb pull - up supp ly voltage on dp 40 - gpio 40 pb3 i/o c p 1ma general purpose i/o pin 41 - usb 41 usbdet i - - usb power detection 42 23 system 42 x12mout o - - 12mhz crystal output. 43 24 system 43 x12min i - - 12 mhz c rystal or ttl compatible clock input . 44 25 44 syste m 45 vss p - - d igital ground of core circuit 45 26 table 2 . pad & pin description
sino wealth sh862 7 0 200 7/2/7 8 / 11 ver 0. 91 pin no. category pad no. pad name type state i dr /i si description ev mc system 46 dis wdt i - - used to dis able watchdog 46 g nd system 47 resetn i ph - system reset 47 27 gpio 48 pb0 i/o c o 1ma general purpose i/o pin 48 28 gpio 49 pb1 i/o c o 1ma general purpose i/o pin 49 29 gpio 50 pa0 i/o cp 1ma general purpose i/o pin 50 30 gpio 51 pa1 i/o cp 1ma general purpose i/o pin 51 31 gpio 52 pa2 i/o cp 1ma general purpose i/o pin 52 32 gpio 53 pa3 i/o cp 1ma general purpose i/o pin 57 33 gpio 54 pa4 i/o cp 1ma general purpose i/o pin 58 34 gpio 55 pa5 i/o cp 1ma general purpose i/o pin 59 35 gpio 56 pa6 i/o cp 1ma general p urpose i/o pin 60 36 gpio 57 pa7 i/o cp 1ma general purpose i/o pin 61 37 ice 58 docd_clk o - 1ma ice interface clock line . 62 - ice 59 docd_dato o - 1ma ice interface data output line . 63 - ice 60 docd_dati i - 1ma ice interface data input line . 64 gn d 61 system 62 vdd18 p - - 1.8 v supply voltage for core circuit 65 38 msi msclk o - mmc/sd clock line gpio 63 pc 3 i/o cp 2ma general purpose i/o pin 66 39 msi mswp i ph mmc/sd card write protection input gpio 64 pc 2 i/o cp 1ma gen eral purpose i/o pin 67 40 msi mscdn i ph mmc/sd card detection input gpio 65 pc1 i/o cp 1ma general purpose i/o pin 68 41 msi mscmd i/o ph mmc/sd command line gpio 66 pc 0 i/o cp 2ma general purpose i/o pin 69 42 system 67 vss p - - d igital ground of made 70 gnd system 68 option i - - system option 71 gnd lcmi 69 lcmcsn o - 1ma lc d chip selection 72 43 efi 70 efrdy i - 1ma nand f lash ready/busy detection 73 44 efi efren o - nand f lash read enable lcmi 71 lcmren o - 2ma lcd read enable 74 45 efi efwen o - nand f lash write enable lcmi 72 lcmwen o - 2ma lcd write enable 75 46 efi 73 efce1n o - 1ma nand f lash chip enable 76 47 efi 74 efce0n o - 1ma nand embedded f lash chip enable 80 48 efi efale o - nand f lash address latch enab le lcmi 75 lcma0 o - 1ma lcd d ata/ c ommand selection 81 49 efi 76 efcle o - 1ma nand f lash command latch enable 82 50 efi efd0 i/o - efi d ata line lcmi 77 lcmd0 i/o - 1 ma lcmi d ata line 83 51 efi efd1 i/o - efi d ata line lcmi 78 lcmd1 i/o - 1 ma lcmi d ata line 84 52 efi efd2 i/o - efi d ata line lcmi 79 lcmd2 i/o - 1 ma lcmi d ata line 85 53 efi efd3 i/o - efi d ata line lcmi 80 lcmd3 i/o - 1 ma lcmi d ata line 86 54 table 3 . pad & pin description (continue)
sino wealth sh862 7 0 200 7/2/7 9 / 11 ver 0. 91 pin no. categor y pad no. pad name type state i dr /i si description ev mc efi efd4 i/o - efi d ata line lcmi lcmd4 i/o - lcmi d ata line msi 81 msd0 i/o ph 2 ma msi d ata line 87 55 efi efd5 i/o - efi d ata line lcmi lcmd5 i/o - lcmi d ata line msi 82 msd1 i/o ph 2 ma msi d ata line 88 56 efi efd6 i/o - efi d ata line lcmi lcmd6 i/o - lcmi d ata line msi 83 msd2 i/o ph 2 ma msi d ata line 89 57 efi efd7 i/o - efi d ata line lcmi lcmd7 i/o - lcmi d ata line msi 84 msd3 i/o ph 2 ma msi d ata line 90 58 dac 85 vinlfm i - - fm input left 91 59 86 system 87 vss p - - d igital ground 92 gnd adc 88 vinmic i - - microphone input 93 60 dac 89 vinrfm i - - fm input right 94 61 90 dac 91 vref dac i - - dac reference voltage 95 62 adc 92 agndadc p - - adc ground 96 dac 93 agnd da c p - - da c ground 97 63 adc 94 avddadc p - - adc supply voltage 98 dac 95 avdddac p - - dac supply voltage 99 64 table 4 . pad & pin description (continue) note: 1. typ e: p ? power, i ? input, o ? output, i/o ? input / output . 2 . state: pl ? pull - low, ph ? pull - high, c p ? configurable pull - low /pull - high , co ? configurable open - drain. 3. ev indicates the ev chip and its package is qfp100. mc indicates the main chip with built - in dc/dc and it s package is lqfp64.
sino wealth sh862 7 0 200 7/2/7 10 / 11 ver 0. 91 4. electrical specifications 4.1. dc characteristics (v dd33 = 3.0 v, v dd18 = 1. 8 v, gnd = 0v, t a = 2 5 c , f osc = 12mhz, unless otherwise specified.) parameter symbol min. typ. max. unit conditions 3.3v operating voltage v dd33 2.8 3.3 3.6 v 3.3v operating current i dd33 - tbd - ma 1.8v operating voltage v dd18 1.6 1.8 2.0 v 1.8v operating current i dd18 - tbd - ma power consumption p - 45 tbd mw @128kbps mp3+lcm+ef high - level output voltage v oh 0.7v dd33 - v dd33 v @v dd =3.0v, i oh = - 2ma low - level output voltage v ol 0 - 0.3v dd33 v @v dd =3.0v, i o l =2 ma high - level input voltage v ih 0.7v dd33 - v dd33 v low - level input voltage v il 0 - 0.3v dd33 v voltage detection range v dr 0.8 - 1.8 v voltage detection resolution v drr es - - ? 0.03 v 3.3v powe r on reset level v por33 2.2 2. 4 2. 6 v 1.8v low voltage reset level v lvr18 1. 2 1. 3 1. 4 v 1.8v power on reset level v por18 0. 8 1. 0 1. 2 v pull - h igh resistor r h 75 k k w pull - l ow resistor r l 75 k k w table 5 . dc characterist ics 4.2. ac characteristics parameter symbol min. typ. max. unit conditions voltage detector setup time t pds 100 tbd us voltage detector response time t pdr 20 tbd us power - on - reset time t rst(por) 40 ms low - voltage - reset time t rst(lvr) 50 us low - v oltage - reset debounce time t lvrdeb 50 us external pin reset period t rst(e p r) 1 ms external pin reset debounce time t eprdeb 150 200 us table 6 . a c characteristics
sino wealth sh862 7 0 200 7/2/7 11 / 11 ver 0. 91 5. package outline 5.1. lqfp64 outline (for main chip package) b e d h d e h e 1 16 48 33 17 32 49 64 see detail f seating plane a a 2 a 1 l l 1 c detail f figure 2 . lqfp64 outline symbol dimensions in inch dimensions in mm a 0.063 (max) 1.60 (max) a 1 0.002 (min.), 0.006(max.) 0.05 (min), 0.15 (max) a 2 0.055 0.002 1.40 0.05 b 0.009 0.002 0.22 0 .05 c 0.004 (min), 0.008 (max) 0.09 (min), 0.20 (max) d 0.394 basic 10.00 basic e 0.394 basic 10.00 basic e 0.020 basic 0.50 basic h d 0.472 basic 12.00 basic h e 0.472 basic 12.00 basic l 0.024 0.006 0.60 0.15 l 1 0.039 ref 1.00 ref table 7 . lqfp64 outline dimension s

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